NextSilicon Unveils Maverick-2 Dataflow Processor Challenging Traditional CPU/GPU Architecture

Revolutionary Dataflow Architecture Emerges

After eight years in development and $303 million across multiple funding rounds, NextSilicon has officially launched its Maverick-2 dataflow engine, according to company announcements. The 64-bit processor represents what analysts suggest could be a fundamental shift in computing architecture, particularly targeting high-performance computing (HPC) applications that remain heavily dependent on 64-bit floating point operations.

Revolutionary Dataflow Architecture Emerges
HPC-First Approach Challenges Convention
Rethinking Fundamental Processor Design
Technical Specifications and Performance Claims
Self-Optimizing Software Architecture
Early Adoption and Performance Benchmarks
Industry Implications

Sources indicate the company is simultaneously introducing a custom RISC-V processor called Arbel, which reportedly will pair with Maverick-2 to create host-accelerator combinations similar to what Nvidia calls “superchips.” This combination creates what the report describes as a truly novel architecture that may appeal to HPC centers worldwide.

HPC-First Approach Challenges Convention

Industry observers note that NextSilicon’s approach differs significantly from conventional processor designers in several key aspects. According to reports, the company has unabashedly positioned itself as HPC-first, a focus that sources indicate hasn’t been seen in compute engine manufacturers for many years.

The Maverick architecture features a multi-tier computing system with a reconfigurable dataflow engine at its core, where the bulk of computing for HPC simulations and models is expected to run. The report states that nothing prevents running AI applications on the processor, though its primary design targets traditional HPC workloads.

Rethinking Fundamental Processor Design

During the Maverick-2 launch presentation, NextSilicon executives highlighted what they describe as fundamental inefficiencies in traditional processor designs. Ilan Tayari, NextSilicon co-founder and vice president of architecture, explained that in typical CPUs, approximately 2% of silicon is dedicated to arithmetic logic units (ALUs) that actually perform mathematical computations., according to industry news

“These solutions can increase performance, but they also have high costs,” Tayari stated, according to the presentation. “They take a lot of silicon real estate, and the mechanism to revert mispredictions has a large negative impact on performance. Today’s high end processors have become complicated and chunky, both physically and practically.”

Analysts suggest that NextSilicon’s approach, termed Intelligent Computing Architecture (ICA), fundamentally reallocates silicon resources. Instead of the reported 98% overhead in traditional CPUs, the Maverick-2 dedicates the majority of its resources to actual computation rather than control overhead and data management.

Technical Specifications and Performance Claims

The Maverick-2 chip reportedly contains 54 billion transistors fabricated using Taiwan Semiconductor Manufacturing Co.’s 5-nanometer process. Sources indicate the monolithic die features four compute regions with 32 RISC-V E-cores positioned on the outer edges. According to the technical documentation, there are 224 compute blocks arranged in a grid pattern, with each block containing hundreds of ALUs.

While NextSilicon hasn’t released exact ALU counts per compute block, estimates suggest the chip could contain tens of thousands to nearly one hundred thousand ALUs. This compares favorably to Nvidia GPUs, which typically feature thousands of CUDA cores rather than tens of thousands of computational units.

Power consumption has reportedly increased since initial projections, with the single-chip Maverick-2 now rated at 400 watts TDP (up from 300 watts) and the dual-chip version for OAM sockets at 750 watts (instead of 600 watts).

Self-Optimizing Software Architecture

What analysts find particularly innovative is the company’s approach to software compilation and optimization. According to reports, existing C, C++, or Fortran code can be automatically mapped to the dataflow architecture without requiring manual porting to CUDA, ROCm, or other parallel computing platforms.

The compiler technology reportedly not only maps code to the ALU blocks but continuously analyzes performance and dynamically optimizes the dataflow without human intervention. “The longer the code runs, the better it gets,” explained Elad Raz, NextSilicon co-founder and CEO, according to the presentation. This automated optimization process represents what sources indicate could be a significant advantage for scientific computing applications where code may run for extended periods.

Early Adoption and Performance Benchmarks

Sandia National Laboratory is expected to be the first production deployment site for Maverick-2 systems, having previously assisted with development of the Maverick-1 proof of concept processor launched in 2022.

Initial benchmark results appear promising, according to company claims. On the GUPS (Giga Updates Per Second) benchmark, which stress tests memory subsystem bandwidth and latency, the Maverick-2 reportedly achieved 32.6 GUPS while consuming 460 watts. NextSilicon claims this represents 22 times faster performance than a CPU and nearly 6 times faster than a GPU, though the specific comparison hardware wasn’t identified in the presentation materials.

The STREAM memory bandwidth benchmark reportedly showed the Maverick-2 delivering 5.2 TB/sec of memory bandwidth, though independent verification of these results isn’t yet available.

Industry Implications

If NextSilicon’s performance claims hold under independent testing, industry observers suggest the Maverick-2 could disrupt the HPC computing landscape. The architecture’s reported ability to automatically optimize existing CPU code for massively parallel execution without developer intervention could significantly lower barriers to accelerated computing.

The technology arrives as HPC centers face increasing pressure to improve computational efficiency while managing power consumption and cooling requirements. NextSilicon’s approach reportedly addresses these challenges by fundamentally rethinking how processors allocate resources between computation and overhead.

As the first production systems prepare for deployment at Sandia, the computing industry will be watching closely to see if NextSilicon’s dataflow architecture can deliver on its promises and establish a viable alternative to traditional CPU and GPU designs for demanding HPC workloads.